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| NJW1321 WIDE BAND VIDEO SWITCH WITH I2C BUS s GENERAL DESCRIPTION 2 The NJW1321 is a Wide Band Video Switch with I C BUS. The NJW1321 includes switch of 4-input 2-output and 6dB amplifier. It is suitable for RGB or Y, Pb, and Pr signal because frequency range is 100MHz. The NJW1321 includes external logic control terminals and external logic discernment terminals. The NJW1321 is suitable for PTV, DTV, PDP and other high quality AV systems. s FEATURES q Operating Voltage 2 q I C BUS Interface q 4-input 2-output 3-Circuits q Wide frequency range s PACKAGE OUTLINE NJW1321FP1 +9.0V 0dB at 100MHz typ. -3dB at 300MHz typ. q Internal 6dB amplifier (Selectable Bypass or 6dB) q External logic discernment terminal q External logic control terminal q Selectable slave address q Power Save Circuit q Bi-CMOS Technology q Package Outline QFP48 s BLOCK DIAGRAM Y/R IN1 Y/R IN2 Y/R IN3 Y/R IN4 6dB 6dB Y/R OUT1 Y/R OUT2 Pb/G IN1 Pb/G IN2 Pb/G IN3 Pb/G IN4 6dB 6dB Pb/G OUT1 Pb/G OUT2 Pr/B IN1 Pr/B IN2 Pr/B IN3 Pr/B IN4 6dB 6dB Pr/B OUT1 Pr/B OUT2 PORT 0 PORT 1 PORT 2 PORT 3 V+ GND VREF BIAS I2C BUS ADDRESS SDA SCL AUX 0 AUX 1 AUX 2 AUX 3 DGND Ver.3 -1- NJW1321 sPIN CONFIGURATION GND Pr IN4 V+ Y IN3 GND Pb IN3 V+ Pr IN3 GND Y IN2 39 Pb IN4 V+ Y IN4 V+ Y OUT1 GND Pb OUT1 GND Pr OUT1 AUX3 AUX2 Y OUT2 AUX1 AUX0 38 25 24 Pb OUT2 PORT0 PORT1 Pr OUT2 V+ VREF DGND GND SDA SCL 48 1 14 15 1. V+ 2. Pb IN2 3. GND 4. Pr IN2 5. GND 6. Y IN1 7. V+ 8. Pb IN1 9. V+ 10. Pr IN1 11. GND 12. PORT3 -2- Pb IN2 GND Pr IN2 GND Y IN1 V+ Pb IN1 V+ Pr IN1 GND PORT3 PORT2 ADR 13. PORT2 14. ADR 15. SCL 16. SDA 17. GND 18. DGND 19. VREG 20. V+ 21. Pr OUT2 22. PORT1 23. PORT 0 24. Pb OUT2 25. AUX0 26. AUX1 27. Y OUT2 28. AUX2 29. AUX3 30. Pr OUT1 31. GND 32. Pb OUT1 33. GND 34. Y OUT1 35. V+ 36. Y IN4 37. V+ 38. Pb IN4 39. GND 40. Pr IN4 41. V+ 42. Y IN3 43. GND 44. Pb IN3 45. V+ 46. Pr IN3 47. GND 48. Y IN2 V+ NJW1321 s ABSOLUTE MAXIMUM RATINGS (Ta=25C) PARAMETER SYMBOL RATINGS UNIT + Supply Voltage V 12.0 V Power Dissipation PD 1875(note) mW Topr -40 to +75 Operating Temperature Range C Tstg -40 to +150 Storage Temperature Range C (Note) At on a board of EIA/JEDEC specification. (76.2 x 114.3 x 1.6mm Two layers, FR-4) s RECOMMENDED OPEARATING CONDITION (Ta=25C) PARAMETER Operating Voltage SYMBOL Vopr + TEST CONDITION MIN. 8.5 TYP. 9.0 MAX. 9.5 UNIT V s ELECTRICAL CHARACTERISTICS (V =9.0V, RL=10K, Ta=25C) qVIDEO PARAMETER Operating Current Maximum Output Voltage Voltage Gain 1 Voltage Gain 2 Frequency Characteristic 1 Frequency Characteristic 2 Frequency Characteristic 3 Frequency Characteristic 4 Cross talk 1 Cross talk 2 Differential Gain Differential Phase S/N qPORT, AUX PARAMETER PORT Input Voltage H PORT Input Voltage M PORY Input Voltage L AUX Output Voltage H AUX Output Voltage M AUX Output Voltage L ADR Input Voltage H ADR Input Voltage L SYMBOL VPTH VPTM VPTL VAUXH VAUXM VAUXL VADRH VADRL TEST CONDITION MIN. 3.5 1.4 0 3.5 1.4 0 3.5 0 TYP. MAX. 5.5 2.4 0.8 5.5 2.4 0.8 5.0 1.0 UNIT V V V V V V V V SYMBOL Icc Vom Gv1 Gv2 Gf1 Gf2 Gf3 Gf4 CTB1 CTB2 DG DP SNv No signal f=100kHz, THD=1% 6dB Mode Vin=100kHz, 1.0Vp-p Sin signal Bypass Mode Vin=100kHz, 1.0Vp-p Sin signal 6dB Mode Vin=100MHz / 100kHz, 1.0Vp-p Sin signal Bypass Mode Vin=100MHz / 100kHz, 1.0Vp-p Sin signal 6dB Mode Vin=300MHz / 100kHz, 1.0Vp-p Sin signal Bypass Mode Vin=300MHz / 100kHz, 1.0Vp-p Sin signal Vin=4.43MHz,1.0Vp-p Sin signal Vin=50MHz,1.0Vp-p Sin signal Vin=1.0Vp-p 10step Video signal Vin=1.0Vp-p 10step Video signal Vin=1.0Vp-p,100% White Video Signal TEST CONDITION MIN. 2.0 6.0 -0.5 TYP. 85 2.5 6.4 0.0 0 0 -3.0 -3.0 -60 -40 0.3 0.3 65 MAX. 100 6.8 0.5 -50 UNIT mA Vp-p dB dB dB dB dB dB dB dB % deg dB -3- NJW1321 s I C BUS BLOCK CHARACTERISTICS (SDA,SCL) PARAMETER High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Low Level Output Voltage (3mA at SDA pin) Maximum Output Current Maximum Clock Frequency Data Change Minimum Waiting Time Data Transfer Start Minimum Waiting Time Low Level Clock Pulse Width High Level Clock Pulse Width Minimum Start Preparation Waiting Time Minimum Data Hold Time Minimum Data Preparation Time Rise Time Fall Time Minimum Stop Preparation Waiting Time I C BUS Load Condition: 2 2 SYMBOL VIH VIL IIH IIL VOL IOL fSCL tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO MIN. 3.0 0 0 -3.0 4.7 4.0 4.7 4.0 4.0 0.0 250 4.0 TYP. - MAX. 5.0 1.5 10 10 0.4 100 3.45 1.0 300 - UNIT V V A A V mA kHz s s s s s s ns s ns s Pull up resistance 4k (Connected to +5V) Load capacitance 200pF (Connected to GND) SDA tBUF tR tF tHD:STA SCL tHD:STA tLOW P S tHD:DAT tHIGH tSU:DAT Sr tSU:STA tSU:STO P -4- NJW1321 sEQUIVALENT CIRCUIT PIN No. NAME 6 8 10 48 2 4 42 44 46 36 38 40 Y IN1 Pb IN1 Pr IN1 Y IN2 Pb IN2 Pr IN2 Y IN3 Pb IN3 Pr IN3 Y IN4 Pb IN4 Pr IN4 FUNCTION INSIDE EQUIVALENT CIRCUIT V+ V+ V+ VOLTAGE Y,Pb,Pr Input RGB Input 150k 100 4.4V V+ V+ 34 32 30 27 24 21 Y OUT1 Pb OUT1 Pr OUT1 Y OUT2 Pb OUT2 Pr OUT2 Y,Pb,Pr Output RGB Output 3.0V 50 V+ V+ 23 22 13 12 PORT0 PORT1 PORT2 PORT3 Logic input terminal 66 100k - V+ V+ V+ 1k 25 26 28 29 AUX0 AUX1 AUX2 AUX3 Auxiliary 3 values voltage output terminal 66 0V 1.9V 5.0V -5- NJW1321 PIN No. NAME FUNCTION INSIDE EQUIVALENT CIRCUIT V+ V+ VREF VOLTAGE 14 ADR Slave address setting terminal 66 - 15 16 SCL SDA I C clock terminal 2 I C data terminal 2 4k - V+ V+ V+ 19 VREF Reference voltage terminal 66 4.8V 48k 1 7 9 20 35 37 41 45 3 5 11 17 31 33 39 43 47 18 V+ Supply voltage terminal - GND Ground terminal - DGND Ground terminal - -6- NJW1321 s DEFINITION OF I C REGISTER I C BUS FORMAT 2 2 MSB LSB MSB LSB MSB LSB S 1bit Slave Address 8bit A 1bit Data 8bit A 1bit Data 8bit A P 1bit 1bit S: Starting Term A: Acknowledge Bit P: Ending Term SLAVE ADDRESS R/W: Set the Write Mode or Read Mode. ADR : Set the Slave Address by "ADR" terminal. Slave Address MSB 1 0 0 0 0 0 ADR x R/W = 0 : Write Mode, ADR = 0/1 1 1 0 0 0 0 1 1 0 0 1 1 0 1 0 0 LSB R/W Hex 94(h) 96(h) 0 0 1 1 0 1 1 1 95(h) 97(h) x R/W = 1 : Read Mode, ADR = 0/1 1 1 0 0 0 0 1 1 CONTROL REGISTER TABLE < Write Mode > No. Data1 Data2 BIT D7 PS1 AUX0 D6 PS2 AUX1 D5 D4 OUT1 AUX2 D3 D2 D1 OUT2 AUX3 D0 < Read Mode > No. Data BIT D7 D6 D5 D4 D3 D2 D1 D0 PORT0 PORT1 PORT2 PORT3 CONTROL REGISTER DEFAULT VALUE Control register default value is all "0". No. Data1 Data2 BIT D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 0 0 D2 0 0 D1 0 0 D0 0 0 -7- NJW1321 !INSTRUCTION CODE POWER SAVE, OUTPUT SETTING No. Data1 BIT D7 PS1 D6 PS2 D5 D4 OUT1 D3 D2 D1 OUT2 D0 *PS1, PS2: Power Save Setting Power Save OUT1 ON OUT2 ON OUT1 ON OUT2 OFF OUT1 OFF OUT2 ON OUT1 OFF OUT2 OFF D7 0 0 1 1 D6 0 1 0 1 ON: Power Save OFF, OFF: Power Save ON (Mute) *OUT1: Output 1 Setting YIN1 YIN2 YIN3 YIN4 Output 1 PbIN1 PbIN2 PbIN3 PbIN4 PrIN1 PrIN2 PrIN3 PrIN4 D5 0 0 1 1 D4 0 1 0 1 Gain 6dB 0dB D3 0 1 *OUT2: Output 2 Setting YIN1 YIN2 YIN3 YIN4 Output 2 PbIN1 PbIN2 PbIN3 PbIN4 PrIN1 PrIN2 PrIN3 PrIN4 D2 0 0 1 1 D1 0 1 0 1 Gain 6dB 0dB D0 0 1 -8- NJW1321 AUX: AUXILIARY SETTING No. Data2 AUX0 L M H AUX1 L M H AUX2 L M H AUX3 L M H BIT D7 AUX0 D7 0 0 1 D5 0 0 1 D3 0 0 1 D1 0 0 1 D6 0 1 1 D4 0 1 1 D2 0 1 1 D0 0 1 1 D6 D5 AUX1 D4 D3 AUX2 D2 D1 AUX3 D0 PORT: PORT SETTING No. Data PORT0 OPEN L M H PORT1 OPEN L M H PORT2 OPEN L M H PORT3 OPEN L M H BIT D7 PORT0 D7 0 0 0 1 D5 0 0 0 1 D3 0 0 0 1 D1 0 0 0 1 D6 0 0 1 1 D4 0 0 1 1 D2 0 0 1 1 D0 0 0 1 1 D6 D5 PORT1 D4 D3 PORT2 D2 D1 PORT3 D0 -9- NJW1321 sTEST CIRCUIT Pb IN4 Y IN4 Y OUT1 Pb OUT1 Pr OUT1 AUX3 AUX2 Y OUT2 AUX1 AUX0 50/75 50/75 10k 10k 10k 10k 10k 10k 10k 10k 1uF + 0.1uF 1uF + 0.1uF 10uF + 0.1uF 10uF + 0.1uF 10uF + 0.1uF 10uF + 0.1uF 38 39 Pr IN4 1uF 37 36 35 34 33 32 31 30 29 28 27 26 25 24 + 10uF 10k 0.1uF + Pb OUT2 40 23 PORT0 50/75 0.1uF 41 Y IN3 1uF 22 PORT1 + 42 21 + 10uF 0.1uF Pr OUT2 10k 50/75 0.1uF 43 Pb IN3 1uF NJW1321 NJW1320 20 + 44 19 + 1uF 50/75 0.1uF 45 Pr IN3 1uF 18 + 46 17 50/75 0.1uF 47 Y IN2 1uF 16 SDA + 48 1 2 + 3 0.1uF 4 + 5 0.1uF 6 + 7 8 + 9 10 + 11 12 13 15 14 SCL 50/75 0.1uF 1uF 1uF 1uF 1uF 1uF 0.1uF 0.1uF 0.1uF PORT3 PORT2 ADR Pb IN2 V+ 50/75 Pr IN2 50/75 Y IN1 50/75 Pb IN1 50/75 Pr IN1 50/75 + 100uF 0.1uF - 10 - NJW1321 sAPPLICATION CIRCUIT Pb IN4 75 Y IN4 75 Y OUT1 Pb OUT1 Pr OUT1 AUX3 AUX2 Y OUT2 AUX1 AUX0 10k 10k 10k 10k 1uF + 0.1uF 1uF + 0.1uF 10uF + 0.1uF 10uF + 0.1uF 10uF + 0.1uF 10uF + 0.1uF 38 39 Pr IN4 1uF 37 36 35 34 33 32 31 30 29 28 27 26 25 24 + 10uF 0.1uF + Pb OUT2 40 23 PORT0 75 0.1uF 41 Y IN3 1uF 22 PORT1 + 42 21 + 10uF 0.1uF Pr OUT2 75 0.1uF 43 Pb IN3 1uF NJW1321 NJW1320 20 + 44 19 + 1uF 75 0.1uF 45 Pr IN3 1uF 18 + 46 17 75 0.1uF 47 Y IN2 75 1uF 16 SDA + 48 1 2 + 3 0.1uF 75 4 + 5 0.1uF 75 6 + 7 8 + 9 10 + 11 12 13 15 14 SCL 0.1uF 1uF 1uF 1uF 1uF 1uF 0.1uF 75 0.1uF 75 0.1uF 75 PORT3 PORT2 ADR Pb IN2 V+ Pr IN2 Y IN1 Pb IN1 Pr IN1 + 100uF 0.1uF - 11 - NJW1321 sTYPICAL CHARACTERISTICS Voltege Gain vs. Frequency 10 0 -10 Gv[dB] -20 -30 0dB 6dB -40 10 6 10 7 10 8 Frequency[Hz] sNOTE Please all connect V+ terminal and GND terminal. When the power supply voltage is not impressing, please do not impress voltage to the ADR terminal. [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. - 12 - |
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